1. Field of the Invention
The present invention relates to a clock signal distributing circuit used in a semiconductor integrated circuit and the like.
2. Description of the Related Art
Conventionally, this type of the clock signal distributing circuit has been employed to decrease the skew of clock signals in a semiconductor integrated circuit, as disclosed, for example, in the Japanese Patent Laid-open No. Hei 4-290261. For a clock signal input means and a plurality of load means whose positions on a semiconductor chip are predetermined, a position of a buffer means is determined and wires are routed from the clock signal input means to the buffer means and from the buffer means to the load means, so as to decrease the skew of clock signals.
FIG. 6 is a chart showing an example for the conventional clock signal distributing circuit. In this clock signal distributing circuit, the position of the buffer means 61 is determined at a point whose X and Y coordinates are X0 and Y0, where X0 and Y0 is the mean value of X and Y coordinates of positions of the load means 62, respectively.
Since the buffer means 61 is placed in the forgoing manner, the difference in wiring distances between the buffer means 61 and each of the load means 62 should be small and the skew of clock signals should also be small.
However, in the conventional clock signal distributing circuit, the transmission delay time of clock signals is not calculated precisely, which is disadvantageous. Since the signal transmission delay time cannot be adjusted precisely, in some cases, the signal transmission delay time and the skew of the signal are not small enough and given conditions for the signal transmission delay and the skew are not satisfied.
This results from the fact that the positions of the buffer means 61 is determined only from the positions of the load means 62, that is, the mean value of the X and Y coordinates.